For example, Japanese Unexamined Patent Application Publication No. 2001-274627 (Patent Document 1) discloses a configuration in which, in order to achieve low power consumption, a current flowing in an inverter circuit in a crystal oscillation circuit is controlled by current sources inserted on a power source voltage side and a ground power source voltage side of the inverter circuit, respectively. Further, Japanese Unexamined Patent Application Publication No. 2006-135739 (Patent Document 2) discloses a configuration in which a variable capacitor is applied to a load capacitor and further a power source voltage of an inverter circuit is set to be variable via a voltage conversion circuit, thereby expanding a variable range of an oscillation frequency in a crystal oscillation circuit. Furthermore, Japanese Unexamined Patent Application Publication No. 10-22734 (Patent Document 3) discloses a configuration in which, in a crystal oscillator including a load capacitor, a quartz crystal unit and others mounted on a multilayer board, an inner layer portion facing a mounting region of the load capacitor, the quartz crystal unit and others is made hollow. By this means, influence of an electrostatic capacitance between patterns or the like is significantly reduced, and it is possible to prevent an oscillation frequency or the like from being largely deviated from a design value.